The present invention relates, in general, to the fabrication of integrated circuits and, in particular, to a method of imaging electrical circuit patterns that includes the incorporation of sub resolution assist features in the photomask layout by which electrical circuit patterns are imaged.
Sub resolution assist features, also known as scattering bars, that are incorporated in photomask layouts provide significant lithographic benefit in the imaging of VLSI circuit patterns. The theory of sub resolution assist features and the mechanics of sub resolution assist feature design are well documented in technical papers and patents. The following are but three examples.
U.S. Pat. No. 5,821,014 relates to a method for providing scattering bars (i.e., sub resolution assist features) for optical proximity effect correction on a mask used in a lithographic process. In this patent, the spacing and characteristics of the scattering bars are adjusted and varied along with main feature edge locations to control the critical dimensions of features that are spaced at distances greater than the minimum pitch of the lithographic process but less than a nominal distance for two feature edges having independent scattering bars.
U.S. Pat. No. 5,447,810 relates to masks used in a lithographic tool utilizing off-axis illumination to provide increased depth of focus and to minimize critical dimension differences between certain features.
xe2x80x9cLithographic Comparison of Assist Feature Design Strategiesxe2x80x9d by Scott M. Mansfield, Lars W. Liebmann, Antoinette F. Molless and Alfred K. Wong IBM Microelectronics dated Mar. 1, 2000 relates to the design tradeoffs in using sub resolution assist features in conjunction with off-axis illumination to reduce proximity effects, while improving the lithographic process window.
Development and optimization of sub resolution assist features are done in a predominantly one-dimensional environment. As shown in FIG. 1, for main details 10, shown by diagonal cross-hatch, the rules for spacings and widths of sub resolution assist features 12, shown by horizontal cross-hatch, are calculated and created for lines of varying pitch (i.e., the distances between main details 10). An edge of a main detail can have two or one or no sub resolution assist features. A space, defined by two edges of two main details, can have four or three or two or one or no sub resolution assist features.
Several problems arise in applying the one dimensional sub resolution assist feature rules to real two dimensional circuit layouts. All these problems can generally be described as layout situations for which no sub resolution assist feature design rules exist. Expanding the sub resolution assist feature design rules to incorporate sub resolution assist feature design instructions for every conceivable layout combination would result in a prohibitively large rule set. It is, therefore, necessary for the sub resolution assist feature design tool to extrapolate sub resolution assist feature design instructions outside of the provided rule set. In some cases, this extrapolation is particularly difficult, such as in the case illustrated in FIG. 2 where a group of vertical main details 14, shown by diagonal cross-hatch, borders against a single horizontal detail 16, also shown by diagonal cross-hatch. The horizontal edges 18a of sub resolution assist features 18, shown by horizontal cross-hatch in FIG. 2, are classified as isolated edges (i.e., there are no sub resolution assist feature proximity neighbors).
The instructions for the design of the vertical sub resolution assist features are directly covered in the one dimensional rules. But these same rules would classify the lower edge of horizontal main detail 16 as a combination of three isolated edge segments (i.e., no neighboring details) where the horizontal edge is opposed by the spaces between the vertical lines and two nested edge segments (i.e., with close neighboring structure) where the horizontal edge is opposed by the vertical line ends. This classification, which is based on the one dimensional rules derived from layout situations in which neighboring edges share significant runlength (e.g., FIG. 1), will introduce an error (i.e., sub resolution assist features of wrong size and spacing will be drawn) in this layout situation that is characterized by a series of short and vastly different proximity environments. The error is further increased by the fact that edge classification operation that determines which sub resolution assist feature rules to apply to each edge segment is unaware of the sub resolution assist features that will be drawn in the horizontal spaces at the time the classification is made.
An example of a layout situation where the extrapolation of the one dimensional tables to the two dimensional layout is done correctly based on the instructions provided, but yields poor sub resolution assist feature coverage (i.e., significant portions of the main detail are opposed by no sub resolution assist features or sub resolution assist features of the wrong size and spacing) is shown in FIG. 3. Based on the one dimensional instructions, an inside corner in main detail 20 will yield concentric L-shaped sub resolution assist features 22a, 22b, 22c and 22d. Over the region A in FIG. 3, the horizontal edge segment of main detail 20 is opposed not by parallel sub resolution assist features but by a combination of perpendicular sub resolution assist features, the corresponding sub resolution assist feature spaces, and some partial horizontal sub resolution assist feature segments. The poor control over the sub resolution assist feature design over region A will result in lithographic process window loss for that segment of main detail 20 and will cause linewidth control problems to the point of complete image loss (i.e., printing problems generally termed necking).
FIG. 4 illustrates another layout situation in which the one dimensional rules result in poor sub resolution assist feature design. The region identified as B in FIG. 4 is characterized by a significant discontinuity in the proximity environment. The bottom horizontal main detail 24 transitions from being a nested main feature to being completely isolated, while the top main detail 26 turns a sharp comer. Further, neither the top horizontal edge 24a of the bottom main detail 24 nor the left vertical edge 26a of the top main detail 26 are visible to each other in the sub resolution assist feature design (i.e., the measurements taken on these edge segments to classify the proximity environment are unaware of the perpendicular edges in the proximity environment). The result of applying the one dimensional rules to this layout situation is that sub resolution assist features suitable for isolated edges (i.e., no neighboring details) are generated for both the left half of the top horizontal edge 24a of the bottom main detail 24 and the left vertical edge 26a of the top main detail 26. The resulting intersecting and overlapping sub resolution assist features cause not only imaging problems to the main details, as described above, but the fact that such a high area percentage is covered by sub resolution assist features will cause significant image intensity loss and will result in images being printed on the wafer by the sub resolution assist features that are nominally intended to be sub resolution.
The only feasible solution to the high density of sub resolution assist features in region B is shown in FIG. 5. Here, all sub resolution assist feature portions that overlapped have been removed from the design, the resulting narrow spaces between sub resolution assist features were then grown to the minimum spacing value allowed by the particular mask and lithography process, and finally any sub resolution assist feature segments that were left with a length below the minimum sub resolution assist feature length after these cleanup steps are removed to avoid mask inspection problems. The result is an area of significant extent in which no sub resolution assist features remain to perform the image enhancement tasks for which they were intended. This, in turn, will result in poor imaging (e.g., small process window and large feature size variation) on all main details bordering region B.
In addition to the layout situations described above, non-parallel projecting edges (i.e., edges between orthogonal lines and angled lines) are very poorly handled by the one dimensional rules.
It is an objective of the present invention to provide a new and improved method for developing a photomask layout by which an electrical circuit is imaged.
It is another objective of the present invention to provide a new and improved method for introducing sub resolution assist features onto a photomask layout by which an electrical circuit is imaged.
It is a further objective of the present invention to provide a new and improved method for introducing sub resolution assist features onto a photomask layout by which an electrical circuit including a transistor and associated wiring is imaged.
To achieve these and other objectives, a method for developing a photomask layout by which an electrical circuit is imaged in accordance with the present invention includes the steps of developing a main electrical circuit in a photomask layout and developing sub resolution assist features in the photomask layout for selected details of the main electrical circuit. The sub resolution assist features are developed by performing the following steps. Selected details of the main electrical circuit undergoing enhancement are sorted according to a predetermined order of importance of enhancement of the selected details of the main electrical circuit to the overall performance of the main electrical circuit. A prioritization of the sub resolution assist features associated with the selected details of the main electrical circuit, based on the predetermined order of importance of the selected details of the main electrical circuit with which the sub resolution assist features are associated, is established. The sub resolution assist features then are incorporated in the photomask layout in accordance with the established prioritization of the sub resolution features.